Arm Cortex-M0+|Kinetis KM1x 50 MHz 32-bit MCUs

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KM1x MCUs enable single-chip one-, two-, and three-phase electricity meters, as well as flow meter and other precision measurement applications.

Includes a powerful analog front end
Provides security, including memory protection, tamper detection, and protection of supplier/user data
Supports high-precision internal voltage reference with low temperature drift
Features a comprehensive enablement suite including reference designs

Data Sheet

Reference Manual

Product Details

Block Diagram

KM1x MCUs

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Features

MCU

High-performance Arm^{^®} Cortex^®-M0 core, up to 50 MHz of core clock frequency
128 KB/64 KB single array flash
Supports v6-M Instruction Set Architecture (ISA) including all 16-bit v7-M instructions plus a number of 32-bit thumb-2 instructions
PLL to generate clocks for AFE
- Input range: 31.25 kHz to 39.0625 kHz
- Output range: 11.72 MHz to 14.65 MHz
FLL to generate core, system and flash clocks
- Input range: 31.25 kHz to 39.0625 kHz
- Output range: 20 MHz to 50 MHz
Flexible modes of operation
Two internal trim-able clock references
- 32 kHz
- 4 MHz

Analog Front End

24-bit sigma delta ADC with 94 dB SNR
Programmable gain amplifier with gains from 1 to 32 with low temperature drift
High precision internal voltage reference with low temperature drift

Security

Tamper detection with time stamping
Random number generator, memory protection unit

Interfaces

High accuracy RTC +5 ppm over temperature range
4x UART, 2x SPI, 2x IIC

Operating Voltage and Temperature Range

Voltage range 1.71 volts - 3.6 volts (without AFE)
Voltage range 2.7 volts - 3.6 volts (with AFE)
Temperature range -40°C to 85°C

Buy/Parametrics

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Design Resources

Design Files

Quick reference to our design files types.

1 design file

Receive the full breakdown. See the product footprint and more in the eCad file.

Symbols and Footprints
Kinetis^® Symbols, Footprints and Models

INTERNALRev 1.0Nov 27, 2017 11:23:001 KBCAD-SYMBOLFOOTPRINTS

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Hardware

Quick reference to our board types.

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Reference Design
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